IntroductionThis blog post describes the progress of the first phase of enabling AMD Turin support in coreboot and porting Gigabyte MZ33-AR1 board. Preparing PSP blobs for AMD platform can be divided into 2 steps:mainboard-agnostic blobs, specific for the CPU siliconmainboard-specific blobs. There might be some new requirements for stitching the PSP blobs for Turin, that was not present earlier in Genoa. Building and runningTo build a bootable coreboot image, we had to go for certain workarounds and omit stichting PSP blobs. A quick peek into the hexdump of the image right at the beginning of the BIOS directory ( $BL2 marker) from which we extracted the APCBs:1 2 3 4 5 6 7 8 9 10 11 12 13 14 01662000 24 42 4c 32 c3 cc 8c 73 22 00 00 00 80 05 00 20 |$BL2...s"...... | 01662010 69 00 00 00 a6 b6 00 00 00 24 66 00 00 00 00 00 |i........$f.....| 01662020 ff ff ff ff ff ff ff ff 68 00 00 00 00 79 00 00 |........h....y..| 01662030 00 db 66 00 00 00 00 00 ff ff ff ff ff ff ff ff |..f.............| 01662040 68 00 80 00 b8 0c 00 00 00 54 67 00 00 00 00 00 |h........Tg.....| 01662050 ff ff ff ff ff ff ff ff 68 00 90 00 a0 05 00 00 |........h.......| 01662060 00 61 67 00 00 00 00 00 ff ff ff ff ff ff ff ff |.ag.............| 01662070 60 00 00 00 00 10 00 00 00 70 67 00 00 00 00 00 |`........pg.....| 01662080 ff ff ff ff ff ff ff ff 60 00 10 00 00 10 00 00 |........`.......| 01662090 00 80 67 00 00 00 00 00 ff ff ff ff ff ff ff ff |..g.............| 016620a0 61 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |a...............| 016620b0 00 00 bc 75 00 00 00 00 62 00 03 00 00 00 34 00 |...u....b.....4.| 016620c0 00 00 cc 00 00 00 00 00 00 00 cc 75 00 00 00 00 |...........u....| 016620d0 63 00 00 00 00 00 0d 00 00 90 67 00 00 00 00 00 |c.........g.....|The APOB entry is at offset 0x016620a0 and its destination address at 0x016620b0 (64bit address) and we see it is equal to 0x75bc0000 .